1. Field of the Invention
The present invention relates to a peripheral driver circuit of a liquid crystal electro-optical device, more specifically, to a peripheral driver circuit of a liquid crystal electro-optical device operated under low power consumption.
2. Description of the Related Art
The liquid crystal electro-optical device of FIG. 29, is well known in the field, and is constructed of a pixel matrix portion 2901, a signal line driver circuit 2902, and a scanning line driver circuit 2903.
In the pixel matrix portion 2901, a scanning line 2904 and a signal line 2905 are arranged in a matrix form. More specifically, in an active matrix type, a pixel thin film transistor (TFT) 2906 is arranged on a cross point, the gate electrode of the pixel TFT 2906 is connected to the scanning line 2904, the source electrode thereof is connected to the signal line 2905, and the drain electrode thereof is connected to the pixel electrode. In general, since a liquid crystal capacitor 2907 defined between the pixel electrode and the counter electrode cannot obtain a large capacitance value, a retaining capacitor 2908 for retaining electric charges is arranged adjacent to the pixel electrode.
When a voltage exceeding a threshold voltage of a pixel TFT is applied to a scanning line, thereby turning on the pixel TFT, a drain electrode of the pixel TFT and a source electrode thereof are brought into a short-circuit condition. Then, the voltage on the signal line is applied to a pixel electrode so that a liquid crystal capacitor and a retaining capacitor are charged. When the pixel TFT is turned off, the drain electrode is under open state, and then the electric charges stored in the liquid crystal capacitor and the retaining capacitor are held until the pixel TFT is subsequently turned on.
The signal line driver circuit 2902 is constructed of a shift register circuit 2909, a buffet circuit 2910, and a sampling circuit 2911. In the shift register circuit 2909, the input signal synchronized with a video signal is input into a terminal 2912, and is sequentially shifted in response to a clock pulse. The output of the shift register circuit 2909 is input via the inverter type buffer circuit 2910 to the sampling circuit 2911.
The sampling circuit 2911 is constructed of an analog switch 2913 and a retaining capacitor 2914. The analog switch 2913 is turned on/off by the buffer circuit 2910. Under the on state, a video signal line 2915 is short-circuited with the retaining capacitor 2914, so that electric charges are stored in the retaining capacitor 2914. The signal line 2905 is connected to the retaining capacitor 2914 to transfer the sampled video signal to the respective pixels.
The scanning line driver circuit 2903 is arranged by a shift register 2916 and the NAND circuit inverter type buffer 2917, and sequentially drives the scanning lines by inputting therein the input signal synchronized with the vertical sync (synchronization) signal and the clock synchronized with the horizontal sync signal.
As the shift register circuit, there are certain possibility that either a clocked inverter 3001 of FIG. 30A or a transmission gate 3002 of FIG. 30B may be employed.
In FIG. 31, there is shown such a case that the clocked inverter structured shift register of FIG. 30A is realized by a CMOS circuit.
As a peripheral driver circuit of a liquid crystal electro-optical device, when a shift register is constructed by using a CMOS circuit on a transparent substrate on which a pixel matrix is formed, there are the following characteristic drawbacks. That is, since a P-channel type TFT and an N-channel type TFT are manufactured, a total number of manufacturing steps is increased. A characteristic of a P-channel type TFT cannot be easily made coincident with that of an N-channel type TFT. An N-channel type TFT may be readily deteriorated. To the contrary, a shift register circuit with a P-channel type TFT and a register in FIG. 32 does not include the above problems caused by the shift register by using the CMOS circuit.
In the shift register circuit using the P-channel type TFT and the register, as shown in FIG. 32, when a P-channel type TFT 3201 is turned on, a power source 3202 is short-circuited via a register 3204 to a ground 3203, so that a through current may flow and thus power consumption would be increased. When the resistance value of the register 3204 is increased so as not to cause the current flow, the discharge operation cannot be easily performed, and a charge from the power source voltage to the ground voltage is delayed. That is, since the frequency characteristic is deteriorated, it is difficult to increase the resistance value. Such high power consumption would surely cause a serious problem when the liquid crystal electro-optical device is utilized in various electronic devices such as portable information devices.
The conventional liquid crystal electro-optical device of FIG. 33 includes a pixel matrix portion 3301, a signal line driver circuit 3302, and a scanning line driver circuit 3303. In the pixel matrix portion 3301, the scanning line 3304 and the signal line 3305 are arranged in a matrix form. In particular, in an active matrix type, a pixel TFT 3306 is arranged at a cross portion, the gate electrode of a pixel TFT 3306 is connected to the scanning line 3304, the source electrode thereof is connected to the signal line 3305, and the drain electrode thereof is connected to the pixel electrode.
When a voltage exceeding the threshold voltage of the pixel TFT is applied to the scanning line, the pixel TFT is turned on. In this state, the drain electrode of the pixel TFT and the source electrode thereof are brought into the short-circuit state, and the voltage on the signal line is applied to the pixel electrode, so that electric charges are stored into the liquid crystal capacitor. When the pixel TFT is turned off, the drain electrode is under open state, and the electric charges stored in the liquid crystal capacitor are held until the pixel TFT is subsequently turned on.
The liquid crystal capacitor 3307 defined between the pixel electrode and the counter electrode cannot have a large value. As a consequence, the electric charges cannot be held by the liquid crystal capacitor 3307 until the pixel TFT is turned on in the next cycle, so that the voltage applied to the liquid crystal is changed, thereby varying gradation. Therefore, the retaining capacitor 3308 for retaining the electric charges is arranged near the pixel electrode. Accordingly, when the pixel TFT is turned on, both the liquid crystal capacitor and the retaining capacitor are charged.
The signal line driver circuit is constructed of a shift register circuit 3401, a buffer circuit 3402, and a sampling circuit 3403 as shown in FIG. 34. In the shift register circuit, the input signal synchronized with the video signal is input and is sequentially shifted in response to the clock pulse. The output of the shift register circuit is input via the inverter type buffer circuit to the sampling circuit.
The sampling circuit includes an analog switch 3404 and an retaining capacitor 3405. The analog switch is turned on/off by the buffer circuit to sample the video signal. The sampled signal is held as the electric charges in the retaining capacitor. The signal line is connected to the retaining capacitor, and the sampled video signal is transferred via this signal line to the respective pixels.
As the signal line driver circuit, a decoder circuit may be utilized instead of the shift register circuit. When the respective pixels and the addresses are combined in one-to-one correspondence and then the video signal is written into the pixel, the corresponding address is input into the signal line driver circuit, and one of these signal lines is selected by the decoder circuit. On the selected signal line, the video signal is sampled by the decode signal and then is held as the electric charge in the retaining capacitor.
Further, as the signal line driver circuit, a decoder circuit and a counter circuit may be used. The clock pulse is counted by the counter circuit, and the output of the counter circuit is used as the address signal. In response to the address signal, the signal line is selected by the decoder circuit to write the sampled video signal into the pixel.
FIG. 35 shows a case that the decoder circuit is used in the signal line driver circuit. Address signal inputs 3501 are selected by a NAND gate 3502, and the output of the NAND gate 3502 is used as the input of an analog switch 3503. The video signal is sampled by the analog switch and the sampled video signal is stored as electric charges in the retaining capacitor 3504. Another case where a decoder circuit and a counter circuit are employed in a signal line driver circuit is shown in FIG. 36. The clock pulse input 3601 is counted by a counter circuit 3602. The output of the counter circuit is selected as the address signal by a NAND gate 3603, and the output of the NAND gate 3603 is input into the analog switch 3604. The video signal is sampled by the analog switch and the sampled video signal is held as electric charges into a retaining capacitor 3605.
In FIG. 37, the scanning line driver circuit is constructed of a shift register 3701 and a NAND circuit inverter type buffer 3702. Both the input signal synchronized with the vertical sync signal and the clock synchronized with the horizontal sync signal are input into the scanning line driver circuit to sequentially drive the scanning line. Also, in this scanning line driver circuit, either a decoder circuit, or a combination of a decoder circuit and a counter circuit may be used instead of the shift register.
As a peripheral driver circuit of a liquid crystal electro-optical device, when a shift register is constructed by using a CMOS circuit on a transparent substrate on which a pixel matrix is fabricated, there are the below-mentioned characteristic drawbacks. That is, since a P-channel type TFT and an N-channel type TFT are manufactured, a total number of manufacturing steps is increased. A characteristic of a P-channel type TFT cannot be easily made coincident with that of an N-channel type TFT. To the contrary, a peripheral circuit using either a P-channel type one conductivity mode TFT, or an N-channel type one conductivity mode TFT with a register does not include the above-described problems as explained in the above-explained peripheral circuit by using the CMOS circuit.
There is shown another circuit that a P-channel type TFT and a resister are used. In FIGS. 38A to 38C, there are a NAND circuit (gate), a NOR circuit, and an inverter circuit as a basic circuit, which may constitute a JK-flip-flop of FIG. 39 and further a 4-bit counter circuit of FIG. 40. The counter circuit produces the respective output signal of a ripple carry 4005, counter bit outputs and inverted outputs 4006 in response to the respective input signals of a power supply (power source) 4001, a clear 4002, a clock 4003 and an enable 4004.
In the case that the peripheral driver circuit using the P-channel type TFT and the resister is manufactured on the transparent substrate on which the pixel matrix has been fabricated, in the circuit of FIG. 38, when the P-channel type TFT is turned on, the power source is short-circuited via the resister to the ground, so that a through current may flow and thus power consumption would be increased. When the resistance value of the resister is increased so as not to cause the current flow, the discharge operation cannot be easily performed, and a change from the power source voltage to the ground voltage is delayed. That is, since the frequency characteristic is deteriorated, it is difficult to increase the resistance value. Such high power consumption may surely cause a serious problem when the liquid crystal electro-optical device is used in various electronic devices such as portable information devices.